<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
<meta http-equiv="X-UA-Compatible" content="IE=9"/>
<meta name="generator" content="Doxygen 1.8.5"/>
<title>spdif: xspdif_hw.h File Reference</title>
<link href="tabs.css" rel="stylesheet" type="text/css"/>
<script type="text/javascript" src="jquery.js"></script>
<script type="text/javascript" src="dynsections.js"></script>
<link href="navtree.css" rel="stylesheet" type="text/css"/>
<script type="text/javascript" src="resize.js"></script>
<script type="text/javascript" src="navtree.js"></script>
<script type="text/javascript">
  $(document).ready(initResizable);
  $(window).load(resizeHeight);
</script>
<link href="doxygen.css" rel="stylesheet" type="text/css" />
<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
</head>
<body>
<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
<div id="titlearea">
<table cellspacing="0" cellpadding="0">
 <tbody>
 <tr style="height: 56px;">
  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.png"/></td>
  <td style="padding-left: 0.5em;">
   <div id="projectname">spdif
   </div>
   <div id="projectbrief">Vitis Drivers API Documentation</div>
  </td>
 </tr>
 </tbody>
</table>
</div>
<!-- end header part -->
<!-- Generated by Doxygen 1.8.5 -->
  <div id="navrow1" class="tabs">
    <ul class="tablist">
      <li><a href="index.html"><span>Overview</span></a></li>
      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
      <li><a href="globals.html"><span>APIs</span></a></li>
      <li><a href="files.html"><span>File&#160;List</span></a></li>
    </ul>
  </div>
</div><!-- top -->
<div id="side-nav" class="ui-resizable side-nav-resizable">
  <div id="nav-tree">
    <div id="nav-tree-contents">
      <div id="nav-sync" class="sync"></div>
    </div>
  </div>
  <div id="splitbar" style="-moz-user-select:none;" 
       class="ui-resizable-handle">
  </div>
</div>
<script type="text/javascript">
$(document).ready(function(){initNavTree('xspdif__hw_8h.html','');});
</script>
<div id="doc-content">
<div class="header">
  <div class="summary">
<a href="#define-members">Macros</a>  </div>
  <div class="headertitle">
<div class="title">xspdif_hw.h File Reference</div>  </div>
</div><!--header-->
<div class="contents">
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:gab9e50bd11dea15481ab6f1c7d89083a8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#gab9e50bd11dea15481ab6f1c7d89083a8">XSPDIF_CLK_4</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:gab9e50bd11dea15481ab6f1c7d89083a8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock divide by 4.  <a href="group__spdif.html#gab9e50bd11dea15481ab6f1c7d89083a8">More...</a><br/></td></tr>
<tr class="separator:gab9e50bd11dea15481ab6f1c7d89083a8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae02f06715593696d6dd15f3a2428bfac"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#gae02f06715593696d6dd15f3a2428bfac">XSPDIF_CLK_8</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:gae02f06715593696d6dd15f3a2428bfac"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock divide by 8.  <a href="group__spdif.html#gae02f06715593696d6dd15f3a2428bfac">More...</a><br/></td></tr>
<tr class="separator:gae02f06715593696d6dd15f3a2428bfac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8f58bf3843cffb58c16ba3c37b6f1a43"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#ga8f58bf3843cffb58c16ba3c37b6f1a43">XSPDIF_CLK_16</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ga8f58bf3843cffb58c16ba3c37b6f1a43"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock divide by 16.  <a href="group__spdif.html#ga8f58bf3843cffb58c16ba3c37b6f1a43">More...</a><br/></td></tr>
<tr class="separator:ga8f58bf3843cffb58c16ba3c37b6f1a43"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacc90df3f63b69ba547aef9449439bdeb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#gacc90df3f63b69ba547aef9449439bdeb">XSPDIF_CLK_24</a>&#160;&#160;&#160;24</td></tr>
<tr class="memdesc:gacc90df3f63b69ba547aef9449439bdeb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock divide by 24.  <a href="group__spdif.html#gacc90df3f63b69ba547aef9449439bdeb">More...</a><br/></td></tr>
<tr class="separator:gacc90df3f63b69ba547aef9449439bdeb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga76f09af6af8a8a42a954d4f3c3b4ead1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#ga76f09af6af8a8a42a954d4f3c3b4ead1">XSPDIF_CLK_32</a>&#160;&#160;&#160;32</td></tr>
<tr class="memdesc:ga76f09af6af8a8a42a954d4f3c3b4ead1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock divide by 32.  <a href="group__spdif.html#ga76f09af6af8a8a42a954d4f3c3b4ead1">More...</a><br/></td></tr>
<tr class="separator:ga76f09af6af8a8a42a954d4f3c3b4ead1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2b1a583d97411e32ac6d37a13c749d0b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#ga2b1a583d97411e32ac6d37a13c749d0b">XSPDIF_CLK_48</a>&#160;&#160;&#160;48</td></tr>
<tr class="memdesc:ga2b1a583d97411e32ac6d37a13c749d0b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock divide by 48.  <a href="group__spdif.html#ga2b1a583d97411e32ac6d37a13c749d0b">More...</a><br/></td></tr>
<tr class="separator:ga2b1a583d97411e32ac6d37a13c749d0b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4c885709bc23885156fa806853159a42"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#ga4c885709bc23885156fa806853159a42">XSPDIF_CLK_64</a>&#160;&#160;&#160;64</td></tr>
<tr class="memdesc:ga4c885709bc23885156fa806853159a42"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock divide by 64.  <a href="group__spdif.html#ga4c885709bc23885156fa806853159a42">More...</a><br/></td></tr>
<tr class="separator:ga4c885709bc23885156fa806853159a42"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Register Map</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Register offsets for the <a class="el" href="struct_x_spdif.html" title="The XSpdif driver instance data. ">XSpdif</a> device. </p>
</div></td></tr>
<tr class="memitem:ga54e62f082a103141123492ce62a09a44"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#ga54e62f082a103141123492ce62a09a44">XSPDIF_GLOBAL_INTERRUPT_ENABLE_OFFSET</a>&#160;&#160;&#160;0x1C</td></tr>
<tr class="memdesc:ga54e62f082a103141123492ce62a09a44"><td class="mdescLeft">&#160;</td><td class="mdescRight">Device Global interrupt enable register.  <a href="group__spdif.html#ga54e62f082a103141123492ce62a09a44">More...</a><br/></td></tr>
<tr class="separator:ga54e62f082a103141123492ce62a09a44"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafecdc424bebe7cf1f779fc5d479c48c3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#gafecdc424bebe7cf1f779fc5d479c48c3">XSPDIF_INTERRUPT_STATUS_REGISTER_OFFSET</a>&#160;&#160;&#160;0x20</td></tr>
<tr class="memdesc:gafecdc424bebe7cf1f779fc5d479c48c3"><td class="mdescLeft">&#160;</td><td class="mdescRight">IP Interrupt Status Register.  <a href="group__spdif.html#gafecdc424bebe7cf1f779fc5d479c48c3">More...</a><br/></td></tr>
<tr class="separator:gafecdc424bebe7cf1f779fc5d479c48c3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2e873c24b76b1f0c5ea5e2067fe96127"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#ga2e873c24b76b1f0c5ea5e2067fe96127">XSPDIF_INTERRUPT_ENABLE_REGISTER_OFFSET</a>&#160;&#160;&#160;0x28</td></tr>
<tr class="memdesc:ga2e873c24b76b1f0c5ea5e2067fe96127"><td class="mdescLeft">&#160;</td><td class="mdescRight">IP interrupt enable Register.  <a href="group__spdif.html#ga2e873c24b76b1f0c5ea5e2067fe96127">More...</a><br/></td></tr>
<tr class="separator:ga2e873c24b76b1f0c5ea5e2067fe96127"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafcc4d1467e4b02bb63d8ed3ca103c384"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#gafcc4d1467e4b02bb63d8ed3ca103c384">XSPDIF_SOFT_RESET_REGISTER_OFFSET</a>&#160;&#160;&#160;0x40</td></tr>
<tr class="memdesc:gafcc4d1467e4b02bb63d8ed3ca103c384"><td class="mdescLeft">&#160;</td><td class="mdescRight">Soft Reset Register.  <a href="group__spdif.html#gafcc4d1467e4b02bb63d8ed3ca103c384">More...</a><br/></td></tr>
<tr class="separator:gafcc4d1467e4b02bb63d8ed3ca103c384"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2fc47b801ec55e2dd7bcebb2bf117422"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#ga2fc47b801ec55e2dd7bcebb2bf117422">XSPDIF_CONTROL_REGISTER_OFFSET</a>&#160;&#160;&#160;0x44</td></tr>
<tr class="memdesc:ga2fc47b801ec55e2dd7bcebb2bf117422"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control Register.  <a href="group__spdif.html#ga2fc47b801ec55e2dd7bcebb2bf117422">More...</a><br/></td></tr>
<tr class="separator:ga2fc47b801ec55e2dd7bcebb2bf117422"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0dcf2448b7e5e551ec1989723967e4b9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#ga0dcf2448b7e5e551ec1989723967e4b9">XSPDIF_STATUS_REGISTER_OFFSET</a>&#160;&#160;&#160;0x48</td></tr>
<tr class="memdesc:ga0dcf2448b7e5e551ec1989723967e4b9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Status Register.  <a href="group__spdif.html#ga0dcf2448b7e5e551ec1989723967e4b9">More...</a><br/></td></tr>
<tr class="separator:ga0dcf2448b7e5e551ec1989723967e4b9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga52d7b2b64993516fbb98d29dd8878be6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#ga52d7b2b64993516fbb98d29dd8878be6">XSPDIF_CHANNEL_STATUS_REGISTER0_OFFSET</a>&#160;&#160;&#160;0x4C</td></tr>
<tr class="memdesc:ga52d7b2b64993516fbb98d29dd8878be6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Audio Channel Status bits 0 to 31.  <a href="group__spdif.html#ga52d7b2b64993516fbb98d29dd8878be6">More...</a><br/></td></tr>
<tr class="separator:ga52d7b2b64993516fbb98d29dd8878be6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga657a7152cbcaf8adee25c4dc9fb6f299"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#ga657a7152cbcaf8adee25c4dc9fb6f299">XSPDIF_CHANNEL_A_USER_DATA_REGISTER0_OFFSET</a>&#160;&#160;&#160;0x64</td></tr>
<tr class="memdesc:ga657a7152cbcaf8adee25c4dc9fb6f299"><td class="mdescLeft">&#160;</td><td class="mdescRight">Channel A user data bits 0 to 31.  <a href="group__spdif.html#ga657a7152cbcaf8adee25c4dc9fb6f299">More...</a><br/></td></tr>
<tr class="separator:ga657a7152cbcaf8adee25c4dc9fb6f299"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1711efa0e12d7e74ddfbc21e4ffd519d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#ga1711efa0e12d7e74ddfbc21e4ffd519d">XSPDIF_CHANNEL_B_USER_DATA_REGISTER0_OFFSET</a>&#160;&#160;&#160;0x7C</td></tr>
<tr class="memdesc:ga1711efa0e12d7e74ddfbc21e4ffd519d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Channel B user data bits 0 to 31.  <a href="group__spdif.html#ga1711efa0e12d7e74ddfbc21e4ffd519d">More...</a><br/></td></tr>
<tr class="separator:ga1711efa0e12d7e74ddfbc21e4ffd519d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Core Configuration Register masks and shifts</div></td></tr>
<tr class="memitem:ga14a20b080d40043f2e576a964ea7d703"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#ga14a20b080d40043f2e576a964ea7d703">XSPDIF_CORE_ENABLE_SHIFT</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:ga14a20b080d40043f2e576a964ea7d703"><td class="mdescLeft">&#160;</td><td class="mdescRight">Is XSPDIF Core Enable bit shift.  <a href="group__spdif.html#ga14a20b080d40043f2e576a964ea7d703">More...</a><br/></td></tr>
<tr class="separator:ga14a20b080d40043f2e576a964ea7d703"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6c809f933049ee2d66fb43f023c3bb32"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#ga6c809f933049ee2d66fb43f023c3bb32">XSPDIF_CORE_ENABLE_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__spdif.html#ga14a20b080d40043f2e576a964ea7d703">XSPDIF_CORE_ENABLE_SHIFT</a>)</td></tr>
<tr class="memdesc:ga6c809f933049ee2d66fb43f023c3bb32"><td class="mdescLeft">&#160;</td><td class="mdescRight">Is XSPDIF Core Enable bit mask.  <a href="group__spdif.html#ga6c809f933049ee2d66fb43f023c3bb32">More...</a><br/></td></tr>
<tr class="separator:ga6c809f933049ee2d66fb43f023c3bb32"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab233d15fdfb78d5162efc06e57a706c6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#gab233d15fdfb78d5162efc06e57a706c6">XSPDIF_FIFO_FLUSH_SHIFT</a>&#160;&#160;&#160;(1)</td></tr>
<tr class="memdesc:gab233d15fdfb78d5162efc06e57a706c6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Is XSPDIF Reset FIFO bit shift.  <a href="group__spdif.html#gab233d15fdfb78d5162efc06e57a706c6">More...</a><br/></td></tr>
<tr class="separator:gab233d15fdfb78d5162efc06e57a706c6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga44d793540b399f583b32940d41614389"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#ga44d793540b399f583b32940d41614389">XSPDIF_FIFO_FLUSH_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__spdif.html#gab233d15fdfb78d5162efc06e57a706c6">XSPDIF_FIFO_FLUSH_SHIFT</a>)</td></tr>
<tr class="memdesc:ga44d793540b399f583b32940d41614389"><td class="mdescLeft">&#160;</td><td class="mdescRight">Is XSPDIF Reset FIFO bit mask.  <a href="group__spdif.html#ga44d793540b399f583b32940d41614389">More...</a><br/></td></tr>
<tr class="separator:ga44d793540b399f583b32940d41614389"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac175833095028d13a1fb8704219cb01f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#gac175833095028d13a1fb8704219cb01f">XSPDIF_CLOCK_CONFIG_BITS_SHIFT</a>&#160;&#160;&#160;(2)</td></tr>
<tr class="memdesc:gac175833095028d13a1fb8704219cb01f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Is XSPDIF clock configuration bits shift.  <a href="group__spdif.html#gac175833095028d13a1fb8704219cb01f">More...</a><br/></td></tr>
<tr class="separator:gac175833095028d13a1fb8704219cb01f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga69580f92443ed12502c008a1457fe1be"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#ga69580f92443ed12502c008a1457fe1be">XSPDIF_CLOCK_CONFIG_BITS_MASK</a>&#160;&#160;&#160;((0xF) &lt;&lt; XSPDIF_CLOCK_CONFIG_BITS_SHIFT)</td></tr>
<tr class="memdesc:ga69580f92443ed12502c008a1457fe1be"><td class="mdescLeft">&#160;</td><td class="mdescRight">Is XSPDIF clock configuration bits mask.  <a href="group__spdif.html#ga69580f92443ed12502c008a1457fe1be">More...</a><br/></td></tr>
<tr class="separator:ga69580f92443ed12502c008a1457fe1be"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga964ad8ea66a86a6ce4c7cf7ff2450dde"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#ga964ad8ea66a86a6ce4c7cf7ff2450dde">XSPDIF_SAMPLE_CLOCK_COUNT_SHIFT</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:ga964ad8ea66a86a6ce4c7cf7ff2450dde"><td class="mdescLeft">&#160;</td><td class="mdescRight">XSPDIF sample clock count shift.  <a href="group__spdif.html#ga964ad8ea66a86a6ce4c7cf7ff2450dde">More...</a><br/></td></tr>
<tr class="separator:ga964ad8ea66a86a6ce4c7cf7ff2450dde"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga20f9c3bca0884af7fdfa9bf0c5f2d86f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#ga20f9c3bca0884af7fdfa9bf0c5f2d86f">XSPDIF_SAMPLE_CLOCK_COUNT_MASK</a>&#160;&#160;&#160;((0X3FF) &lt;&lt; XSPDIF_SAMPLE_CLOCK_COUNT_SHIFT)</td></tr>
<tr class="memdesc:ga20f9c3bca0884af7fdfa9bf0c5f2d86f"><td class="mdescLeft">&#160;</td><td class="mdescRight">XSPDIF sample clock count mask.  <a href="group__spdif.html#ga20f9c3bca0884af7fdfa9bf0c5f2d86f">More...</a><br/></td></tr>
<tr class="separator:ga20f9c3bca0884af7fdfa9bf0c5f2d86f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Interrupt masks and shifts</div></td></tr>
<tr class="memitem:ga1d9df862b59ee96e3e02de1aae228086"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#ga1d9df862b59ee96e3e02de1aae228086">XSPDIF_TX_OR_RX_FIFO_FULL_SHIFT</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:ga1d9df862b59ee96e3e02de1aae228086"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmitter or Receiver FIFO Full Interrupt bit shift.  <a href="group__spdif.html#ga1d9df862b59ee96e3e02de1aae228086">More...</a><br/></td></tr>
<tr class="separator:ga1d9df862b59ee96e3e02de1aae228086"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabe00ee416b556177d910c3e17fb9e873"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#gabe00ee416b556177d910c3e17fb9e873">XSPDIF_TX_OR_RX_FIFO_FULL_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__spdif.html#ga1d9df862b59ee96e3e02de1aae228086">XSPDIF_TX_OR_RX_FIFO_FULL_SHIFT</a>)</td></tr>
<tr class="memdesc:gabe00ee416b556177d910c3e17fb9e873"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmitter or Receiver FIFO Full Interrupt bit mask.  <a href="group__spdif.html#gabe00ee416b556177d910c3e17fb9e873">More...</a><br/></td></tr>
<tr class="separator:gabe00ee416b556177d910c3e17fb9e873"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gade30ebd0405e416cd787ad39b6f3c1cc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#gade30ebd0405e416cd787ad39b6f3c1cc">XSPDIF_TX_OR_RX_FIFO_EMPTY_SHIFT</a>&#160;&#160;&#160;(1)</td></tr>
<tr class="memdesc:gade30ebd0405e416cd787ad39b6f3c1cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmitter or Receiver FIFO Empty Interrupt bit shift.  <a href="group__spdif.html#gade30ebd0405e416cd787ad39b6f3c1cc">More...</a><br/></td></tr>
<tr class="separator:gade30ebd0405e416cd787ad39b6f3c1cc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga01764f0f8e04b295b8ec379e1c039190"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#ga01764f0f8e04b295b8ec379e1c039190">XSPDIF_TX_OR_RX_FIFO_EMPTY_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__spdif.html#gade30ebd0405e416cd787ad39b6f3c1cc">XSPDIF_TX_OR_RX_FIFO_EMPTY_SHIFT</a>)</td></tr>
<tr class="memdesc:ga01764f0f8e04b295b8ec379e1c039190"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmitter or Receiver FIFO Empty Interrupt bit mask.  <a href="group__spdif.html#ga01764f0f8e04b295b8ec379e1c039190">More...</a><br/></td></tr>
<tr class="separator:ga01764f0f8e04b295b8ec379e1c039190"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0480d1e28525b52c86770476d5199ea8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#ga0480d1e28525b52c86770476d5199ea8">XSPDIF_START_OF_BLOCK_SHIFT</a>&#160;&#160;&#160;(2)</td></tr>
<tr class="memdesc:ga0480d1e28525b52c86770476d5199ea8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Start of Block Interrupt bit mask ( in Receive mode)  <a href="group__spdif.html#ga0480d1e28525b52c86770476d5199ea8">More...</a><br/></td></tr>
<tr class="separator:ga0480d1e28525b52c86770476d5199ea8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga85ffec35bf477ccfe1e0cfc949ff7b26"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#ga85ffec35bf477ccfe1e0cfc949ff7b26">XSPDIF_START_OF_BLOCK_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__spdif.html#ga0480d1e28525b52c86770476d5199ea8">XSPDIF_START_OF_BLOCK_SHIFT</a>)</td></tr>
<tr class="memdesc:ga85ffec35bf477ccfe1e0cfc949ff7b26"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmitter or Receiver FIFO Full Interrupt bit shift.  <a href="group__spdif.html#ga85ffec35bf477ccfe1e0cfc949ff7b26">More...</a><br/></td></tr>
<tr class="separator:ga85ffec35bf477ccfe1e0cfc949ff7b26"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacac3ea9e141b8c41d6af146219a01ee2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#gacac3ea9e141b8c41d6af146219a01ee2">XSPDIF_BMC_ERROR_SHIFT</a>&#160;&#160;&#160;(3)</td></tr>
<tr class="memdesc:gacac3ea9e141b8c41d6af146219a01ee2"><td class="mdescLeft">&#160;</td><td class="mdescRight">BMC Error Interrupt bit shift.  <a href="group__spdif.html#gacac3ea9e141b8c41d6af146219a01ee2">More...</a><br/></td></tr>
<tr class="separator:gacac3ea9e141b8c41d6af146219a01ee2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa68d454f0f8827129c0ec744fbf3138f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#gaa68d454f0f8827129c0ec744fbf3138f">XSPDIF_BMC_ERROR_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__spdif.html#gacac3ea9e141b8c41d6af146219a01ee2">XSPDIF_BMC_ERROR_SHIFT</a>)</td></tr>
<tr class="memdesc:gaa68d454f0f8827129c0ec744fbf3138f"><td class="mdescLeft">&#160;</td><td class="mdescRight">BMC Error Interrupt bit mask.  <a href="group__spdif.html#gaa68d454f0f8827129c0ec744fbf3138f">More...</a><br/></td></tr>
<tr class="separator:gaa68d454f0f8827129c0ec744fbf3138f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga50e1fd9807c67cd494b043712940edb6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#ga50e1fd9807c67cd494b043712940edb6">XSPDIF_PREAMBLE_ERROR_SHIFT</a>&#160;&#160;&#160;(4)</td></tr>
<tr class="memdesc:ga50e1fd9807c67cd494b043712940edb6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Preamble error Interrupt bit shift.  <a href="group__spdif.html#ga50e1fd9807c67cd494b043712940edb6">More...</a><br/></td></tr>
<tr class="separator:ga50e1fd9807c67cd494b043712940edb6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4a060f08a718b7727555715810fb6caf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#ga4a060f08a718b7727555715810fb6caf">XSPDIF_PREAMBLE_ERROR_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__spdif.html#ga50e1fd9807c67cd494b043712940edb6">XSPDIF_PREAMBLE_ERROR_SHIFT</a>)</td></tr>
<tr class="memdesc:ga4a060f08a718b7727555715810fb6caf"><td class="mdescLeft">&#160;</td><td class="mdescRight">Preamble error Interrupt bit mask.  <a href="group__spdif.html#ga4a060f08a718b7727555715810fb6caf">More...</a><br/></td></tr>
<tr class="separator:ga4a060f08a718b7727555715810fb6caf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad16dc8a77dde55e1265c9a1f5b09d459"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#gad16dc8a77dde55e1265c9a1f5b09d459">XSPDIF_GINTR_ENABLE_SHIFT</a>&#160;&#160;&#160;(31)</td></tr>
<tr class="memdesc:gad16dc8a77dde55e1265c9a1f5b09d459"><td class="mdescLeft">&#160;</td><td class="mdescRight">Global interrupt enable bit shift.  <a href="group__spdif.html#gad16dc8a77dde55e1265c9a1f5b09d459">More...</a><br/></td></tr>
<tr class="separator:gad16dc8a77dde55e1265c9a1f5b09d459"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad0e21f07fb89aa3b362e4083ca5630dd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#gad0e21f07fb89aa3b362e4083ca5630dd">XSPDIF_GINTR_ENABLE_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__spdif.html#gad16dc8a77dde55e1265c9a1f5b09d459">XSPDIF_GINTR_ENABLE_SHIFT</a>)</td></tr>
<tr class="memdesc:gad0e21f07fb89aa3b362e4083ca5630dd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Global interrupt enable bit mask.  <a href="group__spdif.html#gad0e21f07fb89aa3b362e4083ca5630dd">More...</a><br/></td></tr>
<tr class="separator:gad0e21f07fb89aa3b362e4083ca5630dd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Register access macro definition</div></td></tr>
<tr class="memitem:gac83864972173c1015d34ed8020bf634c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#gac83864972173c1015d34ed8020bf634c">XSpdif_In32</a>&#160;&#160;&#160;Xil_In32</td></tr>
<tr class="memdesc:gac83864972173c1015d34ed8020bf634c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Input Operations.  <a href="group__spdif.html#gac83864972173c1015d34ed8020bf634c">More...</a><br/></td></tr>
<tr class="separator:gac83864972173c1015d34ed8020bf634c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaed24ea3d35e70dcda7745d333425cd1c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#gaed24ea3d35e70dcda7745d333425cd1c">XSpdif_Out32</a>&#160;&#160;&#160;Xil_Out32</td></tr>
<tr class="memdesc:gaed24ea3d35e70dcda7745d333425cd1c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output Operations.  <a href="group__spdif.html#gaed24ea3d35e70dcda7745d333425cd1c">More...</a><br/></td></tr>
<tr class="separator:gaed24ea3d35e70dcda7745d333425cd1c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8a5504bdf152f4699dda951a971b5ce5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#ga8a5504bdf152f4699dda951a971b5ce5">XSpdif_ReadReg</a>(BaseAddress, RegOffset)&#160;&#160;&#160;<a class="el" href="group__spdif.html#gac83864972173c1015d34ed8020bf634c">XSpdif_In32</a>((BaseAddress) + ((u32)RegOffset))</td></tr>
<tr class="memdesc:ga8a5504bdf152f4699dda951a971b5ce5"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro reads a value from a <a class="el" href="struct_x_spdif.html" title="The XSpdif driver instance data. ">XSpdif</a> register.  <a href="group__spdif.html#ga8a5504bdf152f4699dda951a971b5ce5">More...</a><br/></td></tr>
<tr class="separator:ga8a5504bdf152f4699dda951a971b5ce5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga315b6c9b02574277d0f5e66f6bb55888"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spdif.html#ga315b6c9b02574277d0f5e66f6bb55888">XSpdif_WriteReg</a>(BaseAddress, RegOffset, Data)&#160;&#160;&#160;<a class="el" href="group__spdif.html#gaed24ea3d35e70dcda7745d333425cd1c">XSpdif_Out32</a>((BaseAddress) + ((u32)RegOffset), (u32)(Data))</td></tr>
<tr class="memdesc:ga315b6c9b02574277d0f5e66f6bb55888"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro writes a value to a <a class="el" href="struct_x_spdif.html" title="The XSpdif driver instance data. ">XSpdif</a> register.  <a href="group__spdif.html#ga315b6c9b02574277d0f5e66f6bb55888">More...</a><br/></td></tr>
<tr class="separator:ga315b6c9b02574277d0f5e66f6bb55888"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
</div><!-- contents -->
</div><!-- doc-content -->
<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
	<p class="footer">&copy; Copyright 2015-2022 Xilinx, Inc. All Rights Reserved.</p>
	<p class="footer">&copy; Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.</p>
</div>
</body>
</html>
